The present invention relates to a ferroelectric memory device.
As a ferroelectric memory device, an active ferroelectric memory device including 1T/1C cells in which one transistor and one ferroelectric capacitor are disposed in each cell, or including 2T/2C cells in which a reference cell is further disposed in each cell, has been known.
However, since an active ferroelectric memory device has a large memory area in comparison with a flash memory or EEPROM which is known as a nonvolatile memory device in which a memory cell is formed by one element, the capacity cannot be increased.
As a nonvolatile memory device which can be increased in capacity, a ferroelectric memory device in which each memory cell is formed by one ferroelectric capacitor has been proposed (see Japanese Patent Application Laid-open No. 9-116107).
In the ferroelectric memory device in which each memory cell is formed by one ferroelectric capacitor, a plurality of types of voltages must be selectively supplied to a selected word line, unselected word line, selected bit line, and unselected bit line. The number of unselected memory cells is considerably greater than the number of selected memory cells connected with the selected word line and the selected bit line. Therefore, the interconnect load differs between each line to a large extent.
In particular, since the interconnect load of the unselected word line and the unselected bit line is large, a comparatively long period of time is necessary to change the potentials of the unselected word line and the unselected bit line. This results in a decrease in the access speed.